The present disclosure relates generally to the field of integrated circuit fabrication and, more particularly, to fabricating metal-filled openings for submicron integrated circuit technologies.
Semiconductor device geometries continue to dramatically decrease in size, to the extent that existing devices routinely have feature geometries smaller than 90 nm. However, such scaling is accompanied by problems controlling interconnect dishing resulting from planarizing the interconnects after metallization. Those skilled in the art are familiar with the such dishing. The dishing of interconnects and other metal-filled openings is especially prominent when their fabrication employs chemical-mechanical polishing (CMP) to planarize the metal-filled openings.
Another challenge facing the metallization of smaller geometries is providing adequate step coverage and uniformity across the semiconductor substrates. That is, inadequate step coverage or layer uniformity can reduce the quality of the interfaces of inter-metal dielectric (IMD) layers and the metal interconnects, resulting in excessive mechanical and electrical stress between the metal and dielectric layers. Obviously the dishing of interconnects presents an obstacle to obtaining adequate step coverage and layer uniformity. Consequently, interconnect dishing may cause excessive variation in electrical characteristics of the metal interconnects, possibly resulting in IMD failure and, ultimately, device failure.
Metallization employed in the manufacture of integrated circuits for devices with dimensions of 90 nm or less often employs a process generally termed as damascene in which openings such as trenches in an insulative substrate or layer are filled with metal. Copper is frequently employed as the bulk filling interconnect metal. However, copper diffuses easily into many common insulating materials, such as silicon oxide and oxygen containing polymers. Consequently, barrier layers may be incorporated into the damascene process, whereby refractory metals (e.g., TiN, TaN and TiW) are employed as a lining between the copper and the insulative material. However, because existing semiconductor devices may have 30 or more layers of varying composition, the stack of films can suffer internal stress attributable to lattice mismatches where adjacent layers interface. Moreover, such stress may be increased during the manufacturing process, such as from thermal cycling, forces applied during CMP and other manufacturing processes, and the build-up of stress from previously formed layers. As a result, many of the layers may crack or peel, which increases dielectric constants beyond design limits and provides insufficient hardness values, possibly rendering subsequent processing more susceptible to defects. The dishing of any of these layers may contribute to such defects, such that layers formed on interconnect dishing portions may be more susceptible to delamination and stress build-up. Consequently, device yield and performance values may fall below desired levels.
Therefore, a method of forming interconnects and other metal-filled openings is needed to address the problems discussed above.